PLC – brainstorming

ANSARI's Power Line Communication design approach (APLC)

» Posted on 21. Dec 2011

 

 Is it possible to realize a small reliable power line communication interface so low cost, that it could be implemented in any device, which is connected to the power line? 

 

Introduction

Current power line communication solutions can be categorized in three general classes:

  • Broad-Band High-Speed PLC solutions of some Mbit/s (e.g. Home-Plug).
    These solutions generally are expensive because of the heavy digital signal processing demands.
     
  • Narrow-band low-speed PLC solutions (e.g. X10).
    These kinds of PLC solutions are widely in use but have slow data rates of a few hundred bits/s.
     
  • Narrow-band medium-speed PLC solutions (e.g. PRIME alliance).
    Many companies are working on this category of PLC. Commercial and reliable results with acceptable prices are still missing in the market.

ANSARI’s PLC activity focuses on covering this demand. The aim is to develop a low cost narrow-band medium-speed PLC adapter, which is practical for a few hundred meters and doesn’t cost so much by excluding the need of a DSP or MCU to realize the Power Line Communication.

Design Approach

The initial idea of implementing the PLC is to use mixed digital and analog hardware without using any processing unit (DSP or MCU). So, signal modulation and demodulation have to be done by analog circuits and some few functions may be implemented into a programmable logic device (PLD). The desired basic features are:

  • Narrow-band  channel uses frequency ranges of 95 to 148.5 kHz
    (CENELEC EN 50065-1 B,C and D bands)
  • Medium-speed data transfer rate of 1 to 20 kbit/s
  • Low cost, DSP-/MCU-less design with a simple and powerful Analog Front End (AFE)
  • Two separate PLC channels to enable the automatic repeating/bridging or a full duplex connection
     

Implementation

The PLC data transmission media is the AC power line. Based on Telegrapher’s equations the AC power load changes can impact heavily the transmission conditions. As a result the data transmission modulation scheme has to be independent of amplitude. Therefore ideal modulation schemes are techniques based on Phase-Shift-Keying like BPSK or QPSK.

The modulation design principle is to create a sinus wave stream out of a fixed carrier frequency (fc) having four different phase shifts of (0, π/2, π & 3π/2) and multiplexing between these phases based on the input bit stream. The desired transmission wave stream is built using a reference clock with a frequency of 4×fc inside the PLD.

The demodulator is designed based on Coastas Loop Principals. It is intended to use the commonly used implementation of Coastas loop called Polarity Loop. A Coastas loop acts as a carrier recovery system in a coherent BPSK/QPSK demodulator and simultaneously recovers the raw data. The phase shifting, phase detection and parallel to serial conversion sections are handled within the digital section (PLD). The signal filtering, VCO and signal conditionings are handled in analog section.

See the provided block diagrams in this post.

Bandwidth & Bit-Rate

Because of the noisy environment of the AC-Power line, the bandwidth of the communication channel has to be as small as possible to improve the SNR. Therefore, it is decided to limit the channel bandwidth to 10 kHz. As a result, based on Shannon-Hartley theorem, maximum theoretical bit rate in BPSK mode is 10kbit/s and in QPSK is 20kbit/s.

 


References:
  1. Best, R., Phase-Locked Loops, 3rd ed., McGraw-Hill,New York, 1997.
  2. Carlson, A. B., Crilly, P. B., Rutledge, J. C., Communication Systems, 4th ed.,
McGraw-Hill, New York, 2002
  3. Power Line Communications
  4. Shannon–Hartley Theorem
  5. Phase-Shift Keying
  6. Telegrapher’s Equations
  7. PRIME Alliance
  8.  IEEE Standard for Broadband over Power Line

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